1. Field of the Invention
The present invention relates to a semiconductor device equipped with an MIM (Metal-Insulator-Metal) capacitor, particularly to a semiconductor device whose manufacturing process has been simplified.
2. Description of the Related Art
For example, as disclosed in the literature M. Armacost, et. al. “A High Reliability Metal Insulator Metal Capacitor for 0.18 μm Copper Technology” IEDM2000 pp. 157–160′, a lower electrode, a capacitance insulating film, and an upper electrode are laminated on a substrate in this order to form the MIM capacitor when forming a capacitor in the semiconductor device conventionally.
FIG. 1 is a sectional view showing a semiconductor device equipped with a conventional MIM capacitor. As shown in FIG. 1, in the conventional semiconductor device, an oxide film 102 is provided on a substrate 101, and a lower electrode 103 made of metal is provided thereon. Then, a capacitance insulating film 104 is provided on the lower electrode 103, an upper electrode 105 is provided on the capacitance insulating film 104, and a cap film 106 is provided on the upper electrode 105. The upper electrode 105 is connected to wiring 109 via an underlying layer 107 and a via 108, and the lower electrode 103 is connected to wiring 111 via the underlying layer 107 and a via 110. Thus, the lower electrode 103, the capacitance insulating film 104, and the upper electrode 105 form an MIM capacitor 112. Further, the lower electrode 103, the capacitance insulating film 104, the upper electrode 105 and the like are buried in an interlayer insulating film 113.
Further, Japanese Patent Laid-Open No. 2002-222934 publication, for example, discloses a technique where the capacitance insulating film and the upper electrode are formed so as to cover the lower electrode and the MIM capacitor is formed by using not only the top surface but also the sides of the lower electrode.
FIG. 2A is a plan view showing the semiconductor device equipped with the conventional MIM capacitor. FIG. 2B is a sectional view by D—D line shown in FIG. 2A. As shown in FIGS. 2A and 2B, a silicon substrate 121 is provided for the conventional semiconductor device, and a diffusion layer 122 is formed on a part of the surface of the silicon substrate 121. Further, an interlayer insulating film 123 is provided on the silicon substrate 121, and a plug 124 connected to the diffusion layer 122 is formed in the interlayer insulating film 123. Moreover, a lower electrode 125 is provided on the interlayer insulating film 123 so as to connect to the plug 124, and a barrier insulating layer 126 and a high-permittivity film 127 are provided so as to cover the lower electrode 125. Then, the barrier insulating layer 126 and the high-permittivity film 127 form a capacitance insulating film 128. Further, an upper electrode 129 is provided so as to cover the capacitance insulating film 128. Consequently, the lower electrode 125, the capacitance insulating film 128, and the upper electrode 129 form a capacitor 130. According to this prior art, the capacitor can be formed not only on the top surface but also to the sides of the lower electrode 125.
However, the above-described prior art has the following problems. As described above, in the case of forming the capacitor by laminating the lower electrode, the capacitance insulating film, and the upper electrode in this order, the lower electrode can be formed in the wiring layer of the semiconductor device simultaneously with other wiring. However, when a regular interlayer insulating film is used as the capacitance insulating film, the capacitance insulating film becomes too thick because the thickness of the interlayer insulating film is approximately 0.3 to 1.0 μm, and the capacitance value of capacitor is reduced. For this reason, an insulating film having the thickness of approximately 50 nm is specially formed as the capacitance insulating film, and the upper electrode is formed on the capacitance insulating film. As a result, special process for forming the capacitance insulating film and the upper electrode is necessary, the number of masks increases by about 1 to 2 pieces and additional etching process is also required comparing to the case where the capacitor is not formed. Consequently, the manufacturing process of semiconductor device becomes complicate, which leads to an increased manufacturing cost.